Modern integrated circuit memory devices are comprised of a large number of components and conductive connections arranged on a surface of a silicon chip. The capacity of a memory device to store data is governed by the number of components which may be arranged on the silicon chip. The number of components is limited by the physical size or area of the surface of the silicon chip and the density of the components is limited by parasitic electrical effects which occur between proximate components. It is therefore desirable to minimize the number of components of the memory device to maximize the capacity of the memory device to store data.
A conventional memory device is illustrated in FIG. 1. The memory device is a synchronous dynamic random access memory ("SDRAM") 10 which includes an address register 12 that receives either a row address or a column address on an address bus 14. The address bus 14 is generally coupled to a memory controller (not shown in FIG. 1). Typically, a row address is initially received by the address register 12 and applied to a row address multiplexer 18. The row address multiplexer 18 couples the row address to a number of components associated with either of two memory bank arrays 20 and 22 depending upon the state of a bank address bit forming part of the row address. The arrays 20 and 22 are comprised of memory cells arranged in rows and columns. Associated with each of the arrays 20 and 22 is a respective row address latch 26, which stores the row address, and a row decoder 28, which applies various signals to its respective array 20 or 22 as a function of the stored row address. The row address multiplexer 18 also couples row addresses to the row address latches 26 for the purpose of refreshing the memory cells in the arrays 20 and 22. The row addresses are generated for refresh purposes by a refresh counter 30 that is controlled by a refresh controller 32.
After the row address has been applied to the address register 12 and stored in one of the row address latches 26, a column address is applied to the address register 12. The address register 12 couples the column address to a column address latch 40. Depending on the operating mode of the SDRAM 10, the column address is either coupled through a burst counter 42 to a column address buffer 44, or to the burst counter 42, which applies a sequence of column addresses to the column address buffer 44 starting at the column address output by the address register 12. In either case, the column address buffer 44 applies a column address to a column decoder 48, which applies various column signals to respective sense amplifiers and associated column circuits 50 and 52 for the respective arrays 20 and 22.
Data to be read from one of the arrays 20 or 22 are coupled from the arrays 20 or 22, respectively, to a data bus 58 through the column circuit 50 or 52, respectively, and a read data path that includes a data output register 56. Data to be written to one of the arrays 20 or 22 are coupled from the data bus 58 through a write data path, including a data input register 60, to one of the column circuits 50 or 52 where they are transferred to one of the arrays 20 or 22, respectively. A mask register 64 may be used to selectively alter the flow of data into and out of the column circuits 50 and 52 by, for example, selectively masking data to be read from the arrays 20 and 22.
The above-described operation of the SDRAM 10 is controlled by a command decoder 68 responsive to high level command signals received on a control bus 70. These high level command signals, which are typically generated by the memory controller, are a clock enable signal CKE*, a clock signal CLK, a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*, where the "*" designates the signal as active low. The command decoder 68 generates a sequence of command signals responsive to the high level command signals to carry out a function (e.g., a read or a write) designated by each of the high level command signals. These command signals, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these control signals will be omitted.
As mentioned above, read data are coupled from one of the arrays 20 and 22 to the data bus 58 through a read data path that is shown in greater detail in FIG. 2. The read data path 80 is subsumed in the column circuits 50 and 52 and the data output register 56 shown in FIG. 1.
The read data path 80 begins in one of the columns in the array 20. The column includes a complementary pair of digit lines 84 and 86 coupled to the memory cells in the column. A sense amplifier 88 connected between the digit lines 84 and 86 amplifies a differential data signal on the digit lines 84 and 86 in a well-known manner. The differential data signal indicates the presence of a "1" or a "0" in an enabled memory cell in the column. The digit lines 84 and 86 are selectively coupled to a complementary pair of I/O lines 90 and 92 by well known column addressing circuitry, which is not shown in FIG. 2 for purposes of brevity. The I/O lines 90 and 92 are also selectively coupled to the digit lines for a large number of other columns, but these other digit lines have been omitted for purposes of clarity.
The I/O lines 90 and 92 are selectively coupled to a complementary pair of data lines 94 and 96 by first and second pass gates 98 and 100. The pass gates 98 and 100 are located in a multiplexer (not shown) that selectively couples the pair of data lines 94 and 96 to at least one other complementary pair of I/O lines (not shown). A conductive state of each of the pass gates 98 and 100 is controlled by a bank address signal derived from the bank address bit, which is applied to a control line 102 for the pass gate 98 and to a control line 104 for the pass gate 100. Each of the pass gates 98 and 100 receives the bank address signal at a first terminal, and an inverted bank address signal at a second terminal, which is received from one of two inverters 106 and 108, respectively. When the pass gates 98 and 100 are rendered conductive, the differential data signal is coupled from the digit lines 84 and 86 through the I/O lines 90 and 92 to the data lines 94 and 96.
The data lines 94 and 96 are coupled, respectively, to complementary inputs of a DC sense amplifier 110. The DC sense amplifier 110 is a high speed, high gain differential amplifier that amplifies the differential data signal on the data lines 94 and 96 to full CMOS voltage levels. An amplified differential data signal is generated by the DC sense amplifier 110 at complementary outputs and provided to a complementary pair of primary data path lines 112 and 114. The primary data path lines 112 and 114 provide the amplified differential data signal to a complementary pair of inputs of a multiplexer 116. The multiplexer 116 receives amplified differential data signals from other DC sense amplifiers through alternate primary data path lines 118 and 120 and provides a selected amplified differential data signal from complementary outputs to a complementary pair of secondary data path lines 122 and 124. The secondary data path lines 122 and 124 are connected to a complementary pair of inputs in a data output buffer 126, which provides a data signal to a data bus terminal 128 based on the amplified differential data signal.
The components required to support a single array in a memory device, as shown in FIGS. 1 and 2, are numerous and occupy a substantial amount of a silicon chip. It is therefore advantageous to reduce the number of these components required for each array and thereby increase the capacity of the memory device to store data.